1. Field of the Invention
The present invention relates to the design of a memory access structure in a computer system. More particularly, the present invention relates to a memory access structure, which provides fast decoding of memory type information for memory references that fall within a previously accessed module of memory.
2. Related Art
As processors clock speeds continue to increase, memory systems are under increasing pressure to provide data at faster rates to keep pace with the faster processors. This has recently led to the development of new memory chip designs, including page mode and extended data out (EDO) architectures, which achieve a high burst rate and low latencies within a single page of memory. Another recent innovation is to incorporate a synchronous clocked interface into a memory chip, thereby allowing data from within the same page of memory to be clocked out of the memory in a continuous stream using the processor clock. Such memory chips, with clocked interfaces are known as synchronous random access memories.
These new, faster memory chip designs are placing increasing pressure on associated memory controller circuitry to keep pace with the faster memory chips. In particular, memory controllers often include a decode block that must be accessed in a fraction of a memory cycle to retrieve characteristics of a memory module that is presently being accessed. These characteristics may include attributes such as memory speed, memory type and memory size, and are used by the memory controller to generate control signals for the requested memory access. With the faster memory cycle times, it is becoming increasingly harder to access the decode block in the required fraction of a memory cycle. Furthermore, as the number of varieties, sizes and access times supported by a memory controller increases, the amount of time required to decode the memory characteristics also increases.
What is needed is a system that generates characteristics of a memory module being accessed without a significant decoding delay.